module FRM_MPI (
   RESET,

  // interface to global CPU interface
   CPU_CLK,
   CPU_CS,
   CPU_WREN,
   CPU_ADDR,
   CPU_WDATA,
   CPU_RDATA,

  // 
   MPI_PAR_KEEP,
  //
   MPI_SRCM_EN,
   MPI_DSCRM_EN,
   MPI_LOS2AIS_EN,
   MPI_LOC2AIS_EN,
   MPI_LOF2AIS_EN,
   MPI_OOF2AIS_EN,
   MPI_LOS_ALM,
   MPI_LOC_ALM,
   MPI_LOF_ALM,
   MPI_OOF_ALM
   );

input                 RESET;

input                 CPU_CLK;
input                 CPU_CS;
input                 CPU_WREN;
input[7:0]            CPU_ADDR;
input[15:0]           CPU_WDATA;
output reg[15:0]      CPU_RDATA;

output reg[15:0]      MPI_PAR_KEEP;

output reg            MPI_SRCM_EN;
output reg            MPI_DSCRM_EN;

output reg            MPI_LOS2AIS_EN;
output reg            MPI_LOC2AIS_EN;
output reg            MPI_LOF2AIS_EN;
output reg            MPI_OOF2AIS_EN;

input                 MPI_LOS_ALM;
input                 MPI_LOC_ALM;
input                 MPI_LOF_ALM;
input                 MPI_OOF_ALM;


reg[3:0]              CPU_RDATA_NB0;   //lowest nibble of read out data

reg                   INT_ENABLE_LOS;
reg                   INT_ENABLE_LOC;
reg                   INT_ENABLE_LOF;
reg                   INT_ENABLE_OOF;


//******* POH Registers MAP   ********//
//0x40  BIT0          MPI_DSCRM_EN
//0x40  BIT1          MPI_SRCM_EN


always @(posedge RESET or posedge CPU_CLK) begin
   if ( RESET==1'b1 ) begin
      MPI_DSCRM_EN                  <= 1'b0;
      MPI_SRCM_EN                   <= 1'b0;
      MPI_LOS2AIS_EN                <= 1'b1;
      MPI_LOC2AIS_EN                <= 1'b1;
      MPI_LOF2AIS_EN                <= 1'b1;
      MPI_OOF2AIS_EN                <= 1'b1;
      MPI_PAR_KEEP[15:0]            <= 16'h00FF;
      INT_ENABLE_LOS                <= 1'b1;
      INT_ENABLE_LOC                <= 1'b1;
      INT_ENABLE_LOF                <= 1'b1;
      INT_ENABLE_OOF                <= 1'b1;
   end
   else if ( CPU_CS==1'b1 && CPU_WREN==1'b1 ) begin
      case ( CPU_ADDR[7:0] )
      8'h40:  begin
              MPI_SRCM_EN           <= CPU_WDATA[1];
              MPI_DSCRM_EN          <= CPU_WDATA[0];
      end
      8'h41:  begin
              MPI_LOS2AIS_EN        <= CPU_WDATA[3];
              MPI_LOC2AIS_EN        <= CPU_WDATA[2];
              MPI_LOF2AIS_EN        <= CPU_WDATA[1];
              MPI_OOF2AIS_EN        <= CPU_WDATA[0];
      end
      8'h48:  MPI_PAR_KEEP[15:0]    <= CPU_WDATA[15:0];
      8'h51:  begin
              INT_ENABLE_LOS        <= CPU_WDATA[3];
              INT_ENABLE_LOC        <= CPU_WDATA[2];
              INT_ENABLE_LOF        <= CPU_WDATA[1];
              INT_ENABLE_OOF        <= CPU_WDATA[0];
      end
      default: ;
      endcase
   end
end

always @(posedge RESET or posedge CPU_CLK) begin
   if ( RESET==1'b1 ) begin
      CPU_RDATA[15:0]                     <= 16'd0;
   end
   else if ( CPU_CS==1'b1 ) begin
      case ( CPU_ADDR[7:0] )
      8'h40:  CPU_RDATA[15:0]             <= { 14'd0, MPI_SRCM_EN, MPI_DSCRM_EN};
      8'h41:  begin
              CPU_RDATA[15:4]             <= 12'd0;
              CPU_RDATA[3]                <= MPI_LOS2AIS_EN;
              CPU_RDATA[2]                <= MPI_LOC2AIS_EN;
              CPU_RDATA[1]                <= MPI_LOF2AIS_EN;
              CPU_RDATA[0]                <= MPI_OOF2AIS_EN;
      end
      8'h48:  CPU_RDATA[15:0]             <=MPI_PAR_KEEP[15:0];
      8'h50:  begin
              CPU_RDATA[15:4]             <= 12'd0;
              CPU_RDATA[3]                <= MPI_LOS_ALM;
              CPU_RDATA[2]                <= MPI_LOC_ALM;
              CPU_RDATA[1]                <= MPI_LOF_ALM;
              CPU_RDATA[0]                <= MPI_OOF_ALM;
      end
      8'h51:  begin
              CPU_RDATA[15:4]             <= 12'd0;
              CPU_RDATA[3]                <= INT_ENABLE_LOS;
              CPU_RDATA[2]                <= INT_ENABLE_LOC;
              CPU_RDATA[1]                <= INT_ENABLE_LOF;
              CPU_RDATA[0]                <= INT_ENABLE_OOF;
      end
      default:CPU_RDATA[3:0]              <= 4'd0 ;
      endcase
   end
end

endmodule 
